Explain It in 30 Seconds
A modern AI accelerator can perform enormous amounts of computation.
But the processor becomes less useful if it cannot move data to and from memory quickly enough.
CoWoS places compute and HBM close together through a high-density integration structure.
The commercial problem is:
more compute
requires
more memory bandwidthCoWoS helps connect the two.
Where CoWoS Sits in TSMC
HBM stacks
CoWoS is part of TSMC 3DFabric.
It sits after wafer fabrication and before the finished accelerator or system is deployed.
The Problem CoWoS Solves
A large compute die has two related problems.
Memory bandwidth
AI models move huge amounts of data.
Traditional off-package memory connections may not provide enough bandwidth efficiently.
Package scale
A customer may want to combine:
- multiple logic dies;
- HBM stacks;
- chiplets;
- power-management elements.
A conventional package can become too limiting.
CoWoS provides a larger, denser integration environment.
How It Works — Simple Version
The exact implementation differs among CoWoS-S, CoWoS-R and CoWoS-L.
But the high-level structure is:
The interconnect layer lets compute and memory communicate at very high bandwidth over short distances.
CoWoS-S, CoWoS-R and CoWoS-L
CoWoS-S
Uses a silicon interposer and targets very high-performance integration.
CoWoS-R
Uses an RDL-based interposer and has been in volume production since 2023. [S11]
CoWoS-L
Uses local silicon interconnect and RDL-based structures to scale to larger packages.
TSMC says its first 3.5×-reticle CoWoS-L entered volume production in 2024. [S11]
The versions exist because different products need different combinations of:
- size;
- routing density;
- cost;
- mechanical properties;
- performance.
Who Uses CoWoS?
CoWoS is strongly associated with:
- AI accelerators;
- HPC processors;
- networking ASICs;
- products using HBM.
TSMC says generative-AI demand since late 2022 significantly increased demand for CoWoS solutions. [S11]
What CoWoS Depends On
CoWoS depends on more than TSMC logic wafers.
It also depends on:
- HBM supply;
- substrates;
- packaging materials;
- interposer manufacturing;
- testing;
- thermal design;
- customer package design;
- advanced-packaging capacity.
This is why a shortage in packaging capacity can constrain an AI product even when compute wafers are available.
What Depends On CoWoS?
Many large AI and HPC package designs depend on advanced packaging to achieve the required:
- memory bandwidth;
- die count;
- package size;
- interconnect density.
For these products, packaging is part of the compute architecture.
Why CoWoS Matters to TSMC
CoWoS expanded TSMC's value proposition.
Traditional foundry model:
manufacture customer dieCoWoS model:
manufacture die
+
integrate logic and memory
+
help define package-level performanceThat moves TSMC closer to the full system while preserving customer ownership of the product design.
Key Milestones
2012 — Production foundation
TSMC completed CoWoS qualification and transferred the technology into production. [S21]
2023 — CoWoS-R volume production
TSMC says CoWoS-R entered volume production in 2023. [S11]
2024 — Larger CoWoS-L
TSMC's first 3.5×-reticle CoWoS-L entered volume production. [S11]
2026 — Scale continues expanding
TSMC said it was producing 5.5-reticle-size CoWoS and planning much larger future versions for AI compute. [S24]
What Most People Misunderstand
"CoWoS is a chip."
No.
It is a packaging and integration platform.
"HBM is inside the GPU die."
Not generally.
HBM stacks are separate components integrated very close to the compute dies through advanced packaging.
"Packaging only protects the chip."
Not here.
CoWoS affects bandwidth, interconnect and overall system architecture.